The present invention relates to a power-off detection circuit for generating a power-off signal before a supply voltage completely changes to 0 V in the power-off state of an electronic apparatus.
A conventional typical power-off detection circuit is shown in FIG. 1 and comprises resistors R1 and R2, and a comparison circuit CMP. A supply voltage VP is divided by the resistors R1 and R2 to obtain a power source proportional voltage a, and the power source proportional voltage a is inputted in the comparison circuit CMP. Also, the comparison circuit CMP receives a reference voltage Vref showing a level somewhat lower than the supply voltage VP.
The power source proportional voltage a is compared with the reference voltage Vref by the comparison circuit CMP. When the power source proportional voltage a is lower than the reference voltage Vref, a power-off signal P is generated and outputted.
Recently, due to the miniaturization and lightening of the typical electronic apparatus, the power source capacity of many typical apparatus is reduced.
However, in the case where the power source capacity is reduced, it is possible that the above power-off detection circuit may generate and output the power-off signal P even when the power is set ON. For example, in the case where the power source capacity is not sufficiently great and when a control signal S is generated and outputted toward a comparatively heavy load in the electronic apparatus as shown in FIG. 2, the supply voltage VP decreases temporarily.
The level of the power source proportional voltage a divided by the decreased supply voltage VP is lower than that of the reference voltage Vref, and the power-off signal P is generated and outputted.
Accordingly, when the above power-off detection circuit is used in an electronic apparatus having a heavy load such as solenoid of the like, the power source capacity must be made larger than necessary.